Method and apparatus for design of integrated circuits

ABSTRACT

Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/295,241, filed Jun. 1, 2001; U.S. ProvisionalApplication No. 60/295,238, filed Jun. 1, 2001; and U.S. ProvisionalApplication No. 60/295,134, filed Jun. 1, 2001. These applications areincorporated herein by reference.

BACKGROUND

[0002] Architectures for standard cell libraries, as well as gate arraylibraries, have become fairly standard over the years. Most commonarchitectures employ first level power buses that run continuouslythrough the cell. An example of such a cell is shown in FIG. 1, wherethe power rails, 101 and 102 run along the top and bottom edge of thecell. The individual cells, 100 and 103, are placed adjacent to oneanother so that the power rails, 101 and 102, run continuously from oneend of the cell row to the other. In the event that there is a gap inthe cell row, the bus is made to be continuous either by use of a fillercell or by routing a wire through the gap. This power bus can be calledan “explicit bus” since each cell is explicitly connected to each othercell by the actual placement of the cell itself.

[0003] The cell rows themselves are tied together in a grid using otherlevels, as shown in FIG. 2. The first layer busses, 110, are strappedvertically in a second level using a wider bus, 111. The second levelis, in turn, strapped less frequently horizontally by a third layerusing an even wider bus, 112, and so on. In this structured approach,each bus of a given layer typically has the same width, regardless ofthe power requirements of a given section of the grid.

[0004] In FIG. 3, a more complete definition of the common standard celllibrary architecture is given. Fixed width power busses, 120, run infirst level along the top and bottom edge of the cell. These cells arereferred to as “gridded cells” because they are built on a “constructiongrid”, 122, which is typically defined at the via-to-via or via-to-wirespacing for the technology. This construction grid is on the order ofseveral times the gate length of the technology used, typically from 2to 4 times the drawn gate length. The gridded cell must have mostfeatures, including port locations, 121, and cell boundary box, 123, lieon the fixed construction grid. In some cases, these restrictions canmake a given cell larger or more difficult to connect to than a cellbuilt without using any type of construction grid.

[0005] In most standard cell libraries, the contents of the cells mustlie entirely within the cell to avoid creating illegal interactions withadjacent cells. This is illustrated in FIG. 4. Two cells, 130, areplaced next to one another, 138, by placing their boundary boxes, 134and 139, adjacent to one another. The power busses, 131 and 137, jointogether and become continuous. However, the source diffusion areas inthe center, 133 and 135, and the source contacts, 132 and 136, cannot beshared, even though they are electrically connected to the same net.

[0006] In FIG. 5, examples of standard cells are shown, 140, whichcontain “tap contacts”. These are electrical connections either to thewell, as in 142, or to the substrate, as in 143. These ties electricallycouple the appropriate power bus, 141, to the respective well orsubstrate. While this is an electrical requirement, to include the tapcontacts in the cells themselves can use valuable space and make thecell larger or limit the device sizes that can be drawn in the cells.

SUMMARY

[0007] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. The one or more cells can haveone or more virtual buses. The one or more virtual buses include aplurality of ports. The plurality of ports represent a common powersignal. The plurality of ports include at least two power ports on asame layer. The at least two power ports can be separated bysubstantially insulating material in the same layer.

[0008] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. The one or more cells can haveone or more virtual buses. The one or more virtual buses include aplurality of ports. The plurality of ports share a common power signal.The plurality of ports include at least two power ports on a same layer.The at least two power ports can be separated by substantiallyinsulating material in the same layer. The at least two power ports canbe coupled together via one or more electrical paths on one or morelayers of metal.

[0009] In various embodiments, the common power signal includes a fixedvoltage signal. After the at least two power ports are coupled togetherby one or more electrical paths, the plurality of ports representing thecommon power signal can share the common power signal.

[0010] In various embodiments, at least one integrated circuit of theone or more integrated circuits is formed by one or more of a CMOSprocess, a Bi-CMOS process, a bipolar process, a Gallium-Arsenideprocess, and a Silicon-on-Insulator process.

[0011] In various embodiments, the one or more cells can include one ormore of: at least one standard cell, at least one gate array cell, atleast one analog cell, at least one analog mixed signal cell, at leastone analog and digital cell, and at least one functional block cell.

[0012] Some embodiments include one or more integrated circuits designedat least partly with one or more virtual tap cells. The one or morevirtual tap cells include one or more electrical couplings. The one ormore electrical couplings couple to at least one of: one or more wellsand one or more substrates. At least one electrical coupling of the oneor more electrical couplings is positioned entirely outside one or morehierarchies of the one or more virtual tap cells.

[0013] Some embodiments can be characterized by one or more of thefollowing: the at least one of the one or more taps is placed physicallyentirely in one of the one or more virtual tap cells, the at least oneof the one or more taps is placed physically partly in one of the one ormore virtual tap cells, the at least one of the one or more taps isplaced physically partly in one of the one or more other cells, the atleast one electrical coupling is positioned physically on top of the oneor more virtual tap cells, and the at least one electrical coupling ispositioned physically between at least two of the one or more virtualtap cells.

[0014] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. The one or more cells areadapted to have a software tool perform placement of one or morefeatures of the one or more integrated circuits.

[0015] In some embodiments, the placement of at least one of the one ormore features occur primarily to place one or more electrical couplingsto one or more wells and/or substrates.

[0016] In some embodiments, the placement of at least one of the one ormore features occur at a granularity level of one or more electricalcouplings to one or more wells and/or substrates.

[0017] In some embodiments, the software tool includes a router.

[0018] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. The one or more cells having oneor more ports. The one or more ports can be adapted to couple to one ormore metal substantially octagonal via structures.

[0019] In some embodiments, the one or more octagonal via structurescomprises a square via cut and/or a rectangular via cut.

[0020] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. Comprised are significantfeatures including at least one of: signal ports, power ports, and oneor more boundaries of the one or more cells. The significant featuresare freely placed according to a minimum drawing resolution.

[0021] In some embodiments, the minimum drawing resolution correspondsto a layout grid.

[0022] In various embodiments, the significant features include signalports, power ports, and/or one or more boundaries of the one or morecells.

[0023] Some embodiments include one or more integrated circuits designedat least partly with one or more arbitrarily shaped cells. A boundary ofthe arbitrarily shaped cells includes vertices. The vertices are freelyplaced according to a minimum drawing resolution.

[0024] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. At least one of the one or morecells includes at least one of: one or more standard cells, and one ormore gate array cells. The one or more cells are designed to besubstantially coupled by one or more routing wires. The one or morerouting wires are freely placed according to a minimum drawingresolution.

[0025] Some embodiments include one or more integrated circuits designedat least partly with one or more cells. The one or more cells have oneor more ports clipped by an angle. The angle can be about 45 degrees.

[0026] Some embodiments include one or more integrated circuits designedat least partly with a first plurality of one or more cells and a secondplurality of one or more cells. The first plurality of one or more cellshas a first plurality of one or more structures on one or more edges ofthe first plurality of one or more cells. The first plurality of one ormore cells is adapted to be positioned by the second plurality of one ormore cells. The second plurality of one or more cells has a secondplurality of one or more structures on one or more edges of the secondplurality of one or more cells. At least one structure of the firstplurality of one or more structures overlaps at least one structure ofthe second plurality of one or more structures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is an illustration of the traditional method of connectingcell library power buses by abutment.

[0028]FIG. 2 is an illustration of the traditional method ofconstructing a global power grid for cell libraries.

[0029]FIG. 3 is an example of a gridded cell that uses a constructiongrid.

[0030]FIG. 4 is an illustration of cells which cannot share sourceconnections at the cell boundary.

[0031]FIG. 5 is an example of cells which contain taps for well andsubstrate connections.

[0032]FIG. 6 is an example of a cell showing signal ports, power portsand octagonally shaped ports.

[0033]FIG. 7 is an illustration of a rectilinear port and a version ofthe same port with the corners clipped.

[0034]FIG. 8 illustrates how cells in a virtual bus cell library mightlook when placed in a cell row.

[0035]FIG. 9 illustrates how power ports may be connected to one anotherin a virtual bus cell library.

[0036]FIG. 10 illustrates unobstructed interconnections in lowest levelbetween power ports and signal ports when utilizing a virtual bus celllibrary.

[0037]FIG. 11 is an example of a gridless cell that does not use aconstruction grid.

[0038]FIG. 12 illustrates how a cell library may be built to share powerconnections using a common building style.

[0039]FIG. 13 is an example of a virtual tap cell library, since it doesnot contain connections to the well or substrate.

[0040]FIG. 14 illustrates a virtual tap cell library with traditionalpower bus that has been placed into cell rows, with available locationsfor potential tap placements identified.

[0041]FIG. 15 illustrates a virtual tap cell library with virtual powerbus that has been placed into cell rows, with available locations forpotential tap placements identified.

[0042]FIG. 16 is an example of a tap cell that can be used to providewell and substrate connections.

[0043]FIG. 17 is an example of a cell with an arbitrary shape.

[0044]FIG. 18 illustrates how power ports may be connected to oneanother in a virtual bus cell library that uses arbitrary shapes for thecells.

[0045]FIG. 19 is a block diagram showing the progression of anintegrated circuit design to a finished integrated circuit.

DETAILED DESCRIPTION

[0046] Some embodiments include a cell library. Other embodimentsinclude a routing tool adapted to work with the cell library. Yet otherembodiments include an integrated circuit designed with the cell libraryand/or routing tool.

[0047] One embodiment of a cell includes a basic functional block.Another embodiment of a cell includes one or more transistors designedto perform a specific function. Some embodiments of cells are standardcells, gate array cells, sea of gates cells, logic block cells, analogcells, analog digital cells, analog mixed signal cells, functional blockcells, and/or macro cells. One or more of these embodiments can beincluded in a architecture. The architecture can include one or more ofthe following features. The Various embodiments can be used in one moresemiconductor manufacturing processes, such as CMOS, Bi-CMOS, bipolar,gallium arsenide, and/or silicon on insulator.

[0048] Some embodiments use a bus. In some embodiments, a bus describesa metal interconnect line that can be used at least partly, orprimarily, to route a power and/or ground connection to a cell. Someembodiments include one or more of the following buses: power, VDD, VCC,VBB, VSS, ground, and/or GND. In some embodiments, a bus can include afixed voltage supply signal.

[0049] Some embodiments include octagonal vias and/or octagonal contactstructures. A via and contact can be used in a semiconductormanufacturing process to perform an electrical connection between two ormore physical layers. For example, a contact can make an electricalconnection between a metal layer such as a metal1 layer and apolysilicon layer. For example, a via can make an electrical connectionbetween a metal3 layer and a metal4 layer, and so on.

[0050] A via and a contact are most always a square or rectangularopening in a manufacturing process. In some embodiments, an octagonalvia structure consists of a square or rectangular via surrounded byoctagonal metal layers. The advantage of the octagonal metal structureis to allow more freedom and space for the router to place metal linesat 45 degree angles.

[0051] In some embodiments, the interconnecting signal and/or powerports can be optimized by utilizing circular and/or stop-sign(octagonal) shaped ports, contacts, and/or vias in the cells and/or bythe router. By “chamfering” the corners of the signal and/or power portsin the cell, and/or inter-layer contacts, the required spacing toadjacent metal wires running at various angles, for example 90 and/or 45degrees, can be minimized.

[0052] In some embodiments, the use of minimally-sized signal portsand/or power ports can allow the router flexibility in the placement ofconnecting and/or coupling vias, and/or maximize the “empty” space inthe cells for use by the router. In some embodiments, design rules setsmay not allow for minimum and/or stand-alone metal features that can beas small as a contact and/or via. To meet the minimum area rules, insome embodiments, the octagonal and/or circular metal features can bestretched into an elongated octagon and/or circle with an area that canmeet the minimum allowed metal area in design rules. In someembodiments, the area's width can be a minimum, and/or the length can besized as needed.

[0053] In some embodiments, the metal porosity of the cells can bemaximized. Empty space for the router can be left, for example, with asmuch area as possible void of metal.

[0054] In some embodiments, the hierarchy of a cell includes the totalplurality of objects contained within the cell, such that the pluralityof objects may be referred to, and used as, a single object. If afeature is contained within the cell hierarchy, then when the cell isplaced, referenced, and/or used, so is that feature. Each time the cellis used is placed, referenced, and/or used, the feature will have thesame relative placement and orientation with respect to the otherfeatures in the cell hierarchy. If a feature is outside of the hierarchyof the cell, then that feature does not get placed, referenced, and/orused when the cell is placed, referenced and/or used.

[0055] Some embodiments include a virtual bus. One embodiment of a cellmay not include an integrated power bus supply and/or a referencevoltage structure. Some embodiments include a power port. With someembodiments, a port can be used by a router to make a physicalconnection to signals in the cell. Prior to being coupled together viaone or more electrical paths, two or more ports can represent a commonpower signal. After being coupled together via one or more electricalpaths, the two or more power ports can share the common power signal.Power and/or ground reference (and/or other voltage references) can becoupled to the cells other than through a standard structure that isidentical in each cell. In some embodiments, the router can make powerconnections at variable angles to the cell, for example at 0, 45, and/or90 degrees, relative to the cell power ports. Different routerembodiments can have different variable angle capabilities. Some routerembodiments can make such couplings or connections with routedconnections or couplings to the chip power rails. In some embodiments,power ports may not be required to be placed in the same relativeposition within each cell. Cells may contain one or more such powerports, in any layer of metal. In one embodiment, the first level metalcan be that layer.

[0056] When the router couples the power pins of the cells to the chippower rails, some embodiments couple several cells in a local cluster tothe power rails using lower levels of metal, such as the lowest levelsof metal. Several clusters can be coupled together to form largergroups, for example with higher levels of metal. The groups can becoupled together, until the entire chip has power connections. In doingthe power routing, in some embodiments the router can size the powersupply lines to each cell in an optimal way, making the coupling and/orconnection just large enough to supply current to the each cell. In someembodiments, this can be true for sizing the cluster and/or groupconnections and/or couplings. The resulting net in some embodiments canhave wide trunk wires, narrower branch wires, and/or many or most narrowconnections going to the individual cells, or leaves of the net. Lessoptimal power routing strategies can be used in other embodiments.

[0057] In some embodiments, removing the power bus from the cell canresult in reduced cell height, and/or reduced cell area.

[0058] In some embodiments, more free space can be provided for metallevels, such as the first level metals, with routing inside the cells.

[0059] Some embodiments can have, increased metal level porosity, suchas first level metal porosity, over the cell, increased routingcapability, and/or efficiency to the signal ports and/or power ports.For example, a metal level, such as the first level metal, can runvertical wires and/or horizontal wires to adjacent cells above and/orbelow without being blocked by the power bus. In some embodiments, therouter can make the power connections and/or couplings. In someembodiments, one or multiple power nets can be use in one or multiplevoltage domain designs. In some embodiments, the cells can be mixed inthe same cell block. In some embodiments, with low-power designs,sections of logic can be powered off.

[0060] In some embodiments, lesser implementations can use a metallevel, such as second level metal, or a higher level metal, as the powerbus metal. Increased metal level porosity, such as first level metalporosity, may be allowed for.

[0061] Some embodiments include “gridless” cells. In some embodiments,one or more cells may not use a macro-level, construction grid referencestructure for pin placement and/or cell bounding box. Some or all signalports and/or power ports can be located off grid, without reference to aconstruction grid. Some gridless cell embodiments are placed accordingto a minimum drawing resolution, for example the layout grid. In someembodiments, the cell width and/or height can be made as short and/or asnarrow as possible without regard to the construction grid. Someembodiments include arbitrarily shaped cells. For example, not onlyrectangles but arbitrary shapes can be used. In some embodiments, thecell height and width may not be a multiple of the construction grid. Insome embodiments, the ports may not be on the construction grid.

[0062] In some embodiments, a more efficient layout, and/or smallercells can be produced. The size of the cell may not need to be roundedup to a multiple of the construction grid.

[0063] In some embodiments, greater freedom can be allowed in theplacement of port vias.

[0064] Some embodiments can use a standardized, structure on the cellboundaries. Such structures can be overlapped and/or shared by adjacentcells, for example, on the top, bottom, and/or sides. In someembodiments, the standardized structure may be symmetric about the cellboundary. In some embodiments, the router may drop in a spacer betweencells where the standard structure cannot be shared.

[0065] In some embodiments, these structures can be used on the leftand/or right sides of the cell, and/or can include power connections orcouplings to diffusion, which can be used in the cells as a sourcecontact. Adjacent cells in some embodiments can share that structure forsource contacted devices adjacent to the cell edge. In some embodiments,devices can be placed closer to the cell edge than would be allowed by ahalf-spacing rule methodology. Standard structures may be used on thetop and/or bottom of the cells.

[0066] In some embodiments, half diffusion spacing may not be needed onsome cell edges, making for smaller cells. In some embodiments, thenumber of power connections and/or couplings can be minimized to be madeat the chip and/or cluster level.

[0067] Some embodiments include virtual tap cells. In some embodiments,substrate and/or well taps (such as electrical contacts to the bulkmaterial) may not be an integrated part of the cell structure. They canbe smaller by eliminating tap contacts that can be found in the cells.By having the router place taps as requested by the design rules (forexample, on the order of 5 to 10 cell widths), chip overhead requiredfor taps, and/or overall chip area.

[0068] In some embodiments, the router can insert the taps contacts tomeet the design rules. In some embodiments, the router can investigatethe “free” areas that may be available for placement of individual tapcontacts, in and/or among the individual cells, for example after cellplacement and/or before the power routing. In some embodiments, smallareas can be formed between adjacent cells that can accommodateplacement of such a tap contact, which may otherwise be “wasted” space.

[0069] In some embodiments, tap contacts can be inserted by supplying adedicated tap cell. The dedicated tap cell is an example of a featurewhose placement occurs primarily to place one or more electricalcouplings to one or more wells and/or substrates. Other embodiments caninclude just one or more vias and/or contacts. In some embodiments, thetap cell can get placed on intervals between the cells. In someembodiments, the tap cell can allow the router to establish substrateand/or well connections as part of the router's task of routing andplacing cells. In some embodiments, the router can place the taps asrequested by the design rules. In some embodiments, the router may notplace as many as would result from the inclusion of the tap contactswithin the individual cells.

[0070] In some embodiments, once the tap contacts are placed, forexample, as individual contacts and/or as a tap cell, the router canconnect them to the appropriate power rails. In some embodiments, one ormore taps can be routed to a separate net, which may be tied to analternate power rail and/or a set of rails. In some embodiments, thiscan be useful, for example, where the substrate connection from certainlogic sections can be isolated. In some embodiments this can minimizethe propagation of power supply noise from one section of logic toanother. In other embodiments for performance and/or test purposes, aback-bias voltage can be provided to the substrate and/or well that canbe a different voltage than the voltage provided by standard powerrails.

[0071] In some embodiments the router can analyze the layoutpost-placement for places where individual tap contacts can be placedwithin the abutting cell regions. In some embodiments, this can resultin no overhead for the tap contact placement. In some embodiments, thecell library can be post-processed to provide available tie sites to therouter. In some embodiments, the same scheme can be used for placementof diodes for eliminating antenna rule violations.

[0072] In some embodiments, removal of the taps can allow for thepotential of routing the taps on a separate supply rail from the digitallogic supply rail. In some embodiments, this can isolate digital supplyrail noise from analog sections of the chip. In some embodiments, thesubstrate and/or well bias voltage can be raised above and/or below thenormal operating supply rails.

[0073] In some embodiments, this can be useful for lowering the normaldevice threshold voltages, and/or the device leakage, during, forexample, Iddq, quiescent power supply current, production testing.

[0074] By removing the “explicit” power bus and replacing it with a“virtual” power bus, the availability for connecting to other portswithin a cell in greatly enhanced. FIG. 6 shows an example of this typeof cell, 210. The virtual power bus is composed of power ports 211 and212. In some embodiments, the signal ports, 213, and power ports can bedrawn as octagonal structures to maximize the ability of the router torun non-orthogonal wires through the cell. In some embodiments, thesignal ports and power ports can be drawn as polygons with clippedcorners, which approximate octagonal structures at the corners, tomaximize the ability of the router to run non-orthogonal wires throughthe cell. FIG. 7 illustrates this embodiment by showing a rectilinearport, 235, and then a version of the same port, 236, with the cornersclipped, 237.

[0075] In FIG. 8, the cell style of FIG. 6 is used to build a row ofcells, 200, 201, 202 and 203. Power ports, 204 and 205, make up avirtual power bus that will be connected together in upper levels asshown in FIG. 102. Prior to being coupled together via one or moreelectrical paths, power ports 204 and 205 represent a common powersignal. After being coupled together via one or more electrical paths,power ports 204 and 205 share the common power signal. Local powerports, 220, are connected using the lowest level, 222, and relativelynarrow wires. The first layer busses, 222, are then connected in variousdirections in a second or higher level, using a wider bus, 223(interlayer vias shown as 221). The second level, 223, is, in turn,connected by a third higher layer using an even wider bus, 224, and soon. In some embodiments of this non-structured wiring approach, theindividual branches of the power bus may be sized according to the exactpower requirements of those cells in the branch. Some embodiments canhave one or more instances where a higher layer has a narrower bus thana lower layer.

[0076]FIG. 10 illustrates that when cells using the virtual power busarchitecture are placed into cell rows, 250, many of the power ports,251 and 252, can be connected to one another in the lowest level, 256and 257. Some power ports, such as 254, cannot be connected in lowestlevel and must be connected by higher level. In a similar manner,because the fixed power busses do not present blockages, some signalports, such as 255, can be connected locally across the cell rows inlowest level, 258. Other signal ports, such as 253, must be connected inhigher levels.

[0077] By drawing the cells without regard to any type of constructiongrid, such as shown in FIG. 11, the cell area and ability to connect toports may be optimized. Common features such as the cell boundary, 230,power ports, 232 and 233,and signal ports 234, are placed as neededwithout regard to any type of construction grid, as shown by 231 forreference. In this “gridless” cell architecture, all objects may bedrawn on the much smaller drawing grid, which is typically one or twoorders of magnitude smaller than the size of the construction grid.

[0078] The example in FIG. 12 shows a cell library architecture wherethe cells, 240, are built with a common, identical structure on the edgeof the cell. The source diffusion, 242 and 244, as well as the sourcecontacts and power ports, 241 and 245, are placed in the same locationin every cell, straddling the cell boundary 243. When two such cells areplaced adjacent to one another, 246, they will share the sourcediffusion and source contact(s), resulting is a smaller total area forthe two cells.

[0079]FIG. 13 shows examples of two cells, 250 and 251, which do notcontain substrate or well connections (called “taps”) to the powerrails, 252 and 253, and so are referred to as virtual tap cells. Thesecells can be smaller and/or use larger device widths than cells whichcontain tap contacts. In FIG. 14, the cells from FIG. 13 are placed intocell rows. This array of virtual tap cells, 260, happens to be builtusing a cell architecture with an explicit power bus, 261 and 262. Thehighlighted region 263 shows the area into which individual tapconnections to the well can legally be placed. A similar example couldbe shown for placement of substrate contacts. FIG. 15 also shows anarray of virtual tap cells, 265, but with the virtual power busarchitecture, indicated by the presence of power ports, 266 and 267. Thehighlighted region 268 shows the area into which individual tapconnections to the cell can legally be placed. As before, a similarexample could be shown for placement of substrate contacts.

[0080] An alternative to placing individual tap contacts is to use adedicated tap cell as part of the library, as shown in FIG. 16. In thisexample, the cell, 270, includes power ports, 271 and 272, as well astaps to both well, 273, and substrate, 274. Other embodiments have justelectrical couplings to the well or just electrical couplings to thesubstrate. Other embodiments have just vias and/or contacts.

[0081]FIG. 17 shows a cell with an arbitrary shape, where not only arethe major features not on any type of construction grid, 281, but thecell boundary 280 is a polygon with an arbitrary, non-rectangular shape.FIG. 18 shows how these arbitrarily shaped cells, 295, can be connectedusing power ports, 290, and various interconnect levels, 291, 292, 293and 294.

[0082]FIG. 19 is a block diagram showing the progression of anintegrated circuit design to a finished integrated circuit. Librarycells 1910 are processed with a software tool for at least some routingand/or placing 1920. This may be a router. The design in the endproduces an integrated circuit 1930.

[0083] One embodiment of a software tool can be a place and route tool,which places and electrically couples cells to one another.

[0084] Another embodiment of a software tool can be a place and routetool, which places and electrically couples cells to one another, inaddition to providing a way for coupling taps to the substrate and/orwell.

[0085] Another embodiment of a software tool can be a routing tool,which electrically couples cells to one another after the cell have beenplaced.

[0086] Another embodiment of a software tool can be a routing tool,which electrically couples cells to one another after the cell have beenplaced, in addition to providing ways for coupling taps to the substrateand/or well.

[0087] Another embodiment of a software tool can be a floor planningtool, which places and electrically couples cell to one another.

[0088] Another embodiment of a software tool can be a floor planningtool, which places and electrically couples cell to one another, inaddition to providing ways for coupling taps to the substrate and/orwell.

[0089] Another embodiment of a software tool can be a designverification tool, which analyzes the physical layers of the designdatabase and can modify, add and/or subtract features from the designdatabase.

[0090] Another embodiment of a software tool can be a designverification is tool, which analyzes the physical layers of the designdatabase and can modify, add and/or subtract features from the designdatabase in order to electrically couple cell to one another.

[0091] Another embodiment of a software tool can be a designverification tool, which analyzes the physical layers of the designdatabase and can modify, add and/or subtract features from the designdatabase in order to provide a way for coupling taps to the substrateand/or well.

[0092] Another embodiment of a software tool can be a designverification tool, which analyzes the physical layers of the designdatabase and can modify, add and/or subtract features from the designdatabase in order to electrically couple cells to one another and toprovide a way for coupling taps to the substrate and/or well.

[0093] Another embodiment of a software tool can be a layout synthesistool, which can modify, add and/or subtract features from the layoutdatabase.

1. An electrical apparatus, comprising: one or more integrated circuitsdesigned at least partly with one or more cells having one or morevirtual buses, wherein the one or more virtual buses comprise: aplurality of ports representing a common power signal, the plurality ofports including at least two power ports on a same layer, the at leasttwo power ports separated by substantially insulating material in thesame layer.
 2. The apparatus of claim 1, wherein the common power signalincludes a fixed voltage signal.
 3. The apparatus of claim 1, wherein,after the at least two power ports are coupled together by one or moreelectrical paths, the plurality of ports representing the common powersignal share the common power signal.
 4. The apparatus of claim 1,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a CMOS process.
 5. The apparatus of claim 1,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a Bi-CMOS process.
 6. The apparatus of claim 1,wherein an integrated circuit of the integrated circuit is formed by aBipolar process.
 7. The apparatus of claim 1, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aGallium-Arsenide process.
 8. The apparatus of claim 1, wherein at leastone integrated circuit of the one or more integrated circuits is formedby a Silicon-on-Insulator process.
 9. The apparatus of claim 1, whereinthe one or more cells includes at least one standard cell.
 10. Theapparatus of claim 1, wherein the one or more cells includes at leastone gate array cell.
 11. The apparatus of claim 1, wherein the one ormore cells includes at least one analog cell.
 12. The apparatus of claim1, wherein the one or more cells includes at least one analog mixedsignal cell.
 13. The apparatus of claim 1, wherein the one or more cellsincludes at least one analog and digital cell.
 14. The apparatus ofclaim 1, wherein the one or more cells includes at least one functionalblock cell.
 15. An electrical apparatus, comprising: one or moreintegrated circuits designed at least partly with one or more cellshaving one or more virtual buses, wherein the one or more virtual busescomprise: a plurality of ports sharing a common power signal, theplurality of ports including at least two power ports on a same layer,the at least two power ports separated by substantially insulatingmaterial in the same layer, the at least two power ports coupledtogether via one or more electrical paths on one or more layers ofmetal.
 16. The apparatus of claim 15, wherein the common power signalincludes a fixed voltage signal.
 17. The apparatus of claim 15, whereinat least one integrated circuit of the one or more integrated circuitsis formed by a CMOS process.
 18. The apparatus of claim 15, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Bi-CMOS process.
 19. The apparatus of claim 15, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Bipolar process.
 20. The apparatus of claim 15, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Gallium-Arsenide process.
 21. The apparatus of claim 15,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a Silicon-on-Insulator process.
 22. The apparatusof claim 15, wherein the one or more cells includes at least onestandard cell.
 23. The apparatus of claim 15, wherein the one or morecells includes at least one gate array cell.
 24. The apparatus of claim15, wherein the one or more cells includes at least one analog cell. 25.The apparatus of claim 15, wherein the one or more cells includes atleast one analog mixed signal cell.
 26. The apparatus of claim 15,wherein the one or more cells includes at least one analog and digitalcell.
 27. The apparatus of claim 15, wherein the one or more cellsincludes at least one functional block cell.
 28. An electricalapparatus, comprising: one or more integrated circuits designed at leastpartly with one or more virtual tap cells, comprising: one or moreelectrical couplings to at least one of: one or more wells and one ormore substrates, wherein at least one electrical coupling of the one ormore electrical couplings is positioned entirely outside one or morehierarchies of the one or more virtual tap cells.
 29. The apparatus ofclaim 28, wherein the at least one of the one or more taps is placedphysically entirely in one of the one or more virtual tap is cells. 30.The apparatus of claim 28, wherein the at least one of the one or moretaps is placed physically partly in one of the one or more virtual tapcells.
 31. The apparatus of claim 28, wherein the at least one of theone or more taps is placed physically partly in one of the one or moreother cells.
 32. The apparatus of claim 28, wherein the at least oneelectrical couplin g is position ed physically on top of the one or morevirtual tap cells.
 33. The apparatus of claim 28, wherein the at leastone electrical coupling is positioned physically between at least two ofthe one or more virtual tap cells.
 34. The apparatus of claim 28,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a CMOS process.
 35. The apparatus of claim 28,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a Bi-CMOS process.
 36. The apparatus of claim 28,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a Bipolar process.
 37. The apparatus of claim 28,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a Gallium-Arsenide process.
 38. The apparatus ofclaim 28, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Silicon-on-Insulator process.
 39. Theapparatus of claim 28, wherein the one or more cells includes at leastone standard cell.
 40. The apparatus of claim 28, wherein the one ormore cells includes at least one gate array cell.
 41. The apparatus ofclaim 28, wherein the one or more cells includes at least one analogcell.
 42. The apparatus of claim 28, wherein the one or more cellsincludes at least one analog mixed signal cell.
 43. The apparatus ofclaim 28, wherein the one or more cells includes at least one analog anddigital cell.
 44. The apparatus of claim 28, wherein the one or morecells includes at least one functional block cell.
 45. An electricalapparatus, comprising: one or more integrated circuits designed at leastpartly with one or more cells adapted to have a software tool performplacement of one or more features of the one or more integratedcircuits, the placement of at least one of the one or more featuresoccurring primarily to place one or more electrical couplings to one ormore wells.
 46. The apparatus of claim 45, wherein the software toolincludes a router.
 47. The apparatus of claim 45, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aCMOS process.
 48. The apparatus of claim 45, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aBi-CMOS process.
 49. The apparatus of claim 45, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aBipolar process.
 50. The apparatus of claim 45, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aGallium-Arsenide process.
 51. The apparatus of claim 45, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Silicon on Insulator process.
 52. The apparatus of claim 45,wherein the one or more cells includes at least one standard cell. 53.The apparatus of claim 45, wherein the one or more cells includes atleast one gate array cell.
 54. The apparatus of claim 45, wherein theone or more cells includes at least one analog cell.
 55. The apparatusof claim 45, wherein the one or more cells includes at least one analogmixed signal cell.
 56. The apparatus of claim 45, wherein the one ormore cells includes at least one analog and digital cell.
 57. Theapparatus of claim 45, wherein the one or more cells includes at leastone functional block cell.
 58. An electrical apparatus, comprising: oneor more integrated circuits designed at least partly with one or morecells adapted to have a software tool perform placement of one or morefeatures of the one or more integrated circuits, the placement of atleast one of the one or more features occurring at a granularity levelof one or more electrical couplings to one or more wells.
 59. Theapparatus of claim 58, wherein the software tool includes a router. 60.The apparatus of claim 58, wherein at least one integrated circuit ofthe one or more integrated circuits is formed by a CMOS process.
 61. Theapparatus of claim 58, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Bi-CMOS process.
 62. Theapparatus of claim 58, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Bipolar process.
 63. Theapparatus of claim 58, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Gallium-Arsenide process.64. The apparatus of claim 58, wherein at least one integrated circuitof the one or more integrated circuits is formed by a Silicon onInsulator process.
 65. The apparatus of claim 58, wherein the one ormore cells includes at least one standard cell.
 66. The apparatus ofclaim 58, wherein the one or more cells includes at least one gate arraycell.
 67. The apparatus of claim 58, wherein the one or more cellsincludes at least one analog cell.
 68. The apparatus of claim 58,wherein the one or more cells includes at least one analog mixed signalcell.
 69. The apparatus of claim 58, wherein the one or more cellsincludes at least one analog and digital cell.
 70. The apparatus ofclaim 58, wherein the one or more cells includes at least one functionalblock cell.
 71. An electrical apparatus, comprising: one or moreintegrated circuits designed at least partly with one or more cellsadapted to have a software tool perform placement of one or morefeatures of the one or more integrated circuits, the placement of atleast one of the one or more features occurring primarily to place oneor more electrical couplings to one or more substrates.
 72. The claim of71, wherein the software tool includes a router.
 73. The apparatus ofclaim 71, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a CMOS process.
 74. The apparatus ofclaim 71, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Bi-CMOS process.
 75. The apparatus ofclaim 71, wherein at least one integrated circuit of lo the one or moreintegrated circuits is formed by a Bipolar process.
 76. The apparatus ofclaim 71, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Gallium-Arsenide process.
 77. Theapparatus of claim 71, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Silicon-on-Insulatorprocess.
 78. The apparatus of claim 71, wherein the one or more cellsincludes at least one standard cell.
 79. The apparatus of claim 71,wherein the one or more cells includes at least one gate array cell. 80.The apparatus of claim 71, wherein the one or more cells includes atleast one analog cell.
 81. The apparatus of claim 71, wherein the one ormore cells includes at least one analog mixed signal cell.
 82. Theapparatus of claim 71, wherein the one or more cells includes at leastone analog and digital cell.
 83. The apparatus of claim 71, wherein theone or more cells includes at least one functional block cell.
 84. Anelectrical apparatus, comprising: one or more integrated circuitsdesigned at least partly with one or more cells adapted to have asoftware tool perform placement of one or more features of the one ormore integrated circuits, the placement of at least one of the one ormore features occurring at a granularity level of one or more electricalcouplings to one or more substrates.
 85. The apparatus of claim 84,wherein the software tool includes a router.
 86. The apparatus of claim84, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a CMOS process.
 87. The apparatus ofclaim 84, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Bi-CMOS process.
 88. The apparatus ofclaim 84, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Bipolar process.
 89. The apparatus ofclaim 84, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Gallium-Arsenide process.
 90. Theapparatus of claim 84, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Silicon-on-Insulatorprocess.
 91. The apparatus of claim 84, wherein the one or more cellsincludes at least one standard cell.
 92. The apparatus of claim 84,wherein the one or more cells includes at least one gate array cell. 93.The apparatus of claim 84, wherein the one or more cells includes atleast one analog cell.
 94. The apparatus of claim 84, wherein the one ormore cells includes at least one analog mixed signal cell.
 95. Theapparatus of claim 84, wherein the one or more cells includes at leastone analog and digital cell.
 96. The apparatus of claim 84, wherein theone or more cells includes at least one functional block cell.
 97. Anelectrical apparatus, comprising: one or more integrated circuitsdesigned at least partly with one or more cells, the one or more cellshaving one or more ports, the one or more ports adapted to couple to oneor more metal substantially octagonal via structures.
 98. The apparatusof claim 97, wherein the one or more substantially octagonal viastructures comprises a square via cut.
 99. The apparatus of claim 97,wherein the one or more substantially octagonal via structures comprisesa rectangular via cut.
 100. The apparatus of claim 97, wherein at leastone integrated circuit of the one or more integrated circuits is formedby a CMOS process.
 101. The apparatus of claim 97, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aBi-CMOS process.
 102. The apparatus of claim 97, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aBipolar process.
 103. The apparatus of claim 97, wherein at least oneintegrated circuit of the one or more integrated circuits is formed by aGallium Arsenide process.
 104. The apparatus of claim 97, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Silicon-on-Insulator process.
 105. The apparatus of claim97, wherein the one or more cells includes at least one standard cell.106. The apparatus of claim 97, wherein the one or more cells includesat least one gate array cell.
 107. The apparatus of claim 97, whereinthe one or more cells includes at least one analog cell.
 108. Theapparatus of claim 97, wherein the one or more cells includes at leastone analog mixed signal cell.
 109. The apparatus of claim 97, whereinthe one or more cells includes at least one analog and digital cell.110. The apparatus of claim 97, wherein the one or more cells includesat least one functional block cell.
 111. An electrical apparatus,comprising: one or more integrated circuits designed at least partlywith one or more cells, comprising significant features including atleast one of: signal ports, power ports, and one or more boundaries ofthe one or more cells, wherein the significant features are freelyplaced according to a minimum drawing resolution.
 112. The apparatus ofclaim 111, wherein the minimum drawing resolution corresponds to alayout grid.
 113. The apparatus of claim 111, wherein the significantfeatures include signal ports.
 114. The apparatus of claim 111, whereinthe significant features include power ports.
 115. The apparatus ofclaim 111, wherein the significant features include one or moreboundaries of the one or more cells.
 116. The apparatus of claim 111,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a CMOS process.
 117. The apparatus of claim 111,wherein at least one integrated circuit of the one or more integratedcircuits is formed by a Bi-CMOS process.
 118. The apparatus of claim111, wherein at least one integrated circuit of the one or moreintegrated circuits is formed by a Bipolar process.
 119. The apparatusof claim 111, wherein an integrated circuit i of the integrated circuitdesign is formed by a Gallium-Arsenide process.
 120. The apparatus ofclaim 111, wherein an integrated circuit i of the integrated circuitdesign s formed by a Silicon-on-Insulator process.
 121. The apparatus ofclaim 111, wherein the one or more cells includes at least one standardcell.
 122. The apparatus of claim 111, wherein the one or more cellsincludes at least one gate array cell.
 123. The apparatus of claim 111,wherein the one or more cells includes at least one analog cell. 124.The apparatus of claim 1 11, wherein the one or more cells includes atleast one analog mixed signal cell.
 125. The apparatus of claim 1 11,wherein the one or more cells includes at least one analog and digitalcell.
 126. The apparatus of claim 111, wherein the one or more cellsincludes at least one functional block cell.
 127. An electricalapparatus, comprising: one or more integrated circuits designed at leastpartly with one or more arbitrarily shaped cells, wherein the boundaryof the arbitrarily shaped cells include vertices, the vertices adaptedto be freely placed according to a minimum drawing resolution.
 128. Theapparatus of claim 127, wherein the minimum drawing resolutioncorresponds to a layout grid.
 129. The apparatus of claim 127, whereinat least one integrated circuit of the one or more integrated circuitsis formed by a CMOS process.
 130. The apparatus of claim 127, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Bi-CMOS process.
 131. The apparatus of claim 127, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Bipolar process.
 132. The apparatus of claim 127, wherein anintegrated circuit of the integrated circuit design is formed by aGallium-Arsenide process.
 133. The apparatus of claim 127, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Silicon-on-Insulator process.
 134. The apparatus of claim127, wherein the one or more cells includes at least one standard cell.135. The apparatus of claim 127, wherein the one or more cells includesat least one gate array cell.
 136. The apparatus of claim 127, whereinthe one or more cells includes at least one analog cell.
 137. Theapparatus of claim 127, wherein the one or more cells includes at leastone analog mixed signal cell.
 138. The apparatus of claim 127, whereinthe one or more cells includes at least one analog and digital cell.139. The apparatus of claim 127, wherein the one or more cells includesat least one functional block cell.
 140. An electrical apparatus,comprising: one or more integrated circuits designed at least partlywith one or more cells, at least one of the one or more cells includingat least one of: one or more standard cells, and one or more gate arraycells, wherein the one or more cells are designed to be substantiallycoupled by one or more routing wires freely placed according to aminimum drawing resolution.
 141. The apparatus of claim 140, wherein theminimum drawing resolution corresponds to a layout grid.
 142. Theapparatus of claim 140, wherein at least one integrated circuit of theone or more integrated circuits is formed by a CMOS process.
 143. Theapparatus of claim 140, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Bi-CMOS process.
 144. Theapparatus of claim 140, wherein the integrated circuit of the integratedcircuit design is formed by a Bipolar process.
 145. The apparatus ofclaim 140, wherein the integrated circuit of the integrated circuitdesign is formed by a Gallium-Arsenide process.
 146. The apparatus ofclaim 140, wherein the integrated circuit of the integrated circuitdesign is formed by a Silicon-on-Insulator process.
 147. The apparatusof claim 140, wherein the one or more cells includes at least onestandard cell.
 148. The apparatus of claim 140, wherein the one or morecells includes at least one gate array cell.
 149. An electricalapparatus, comprising: one or more integrated circuits designed at leastpartly with one or more cells, the one or more cells having one or moreports clipped by an angle.
 150. The apparatus of claim 149, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a CMOS process.
 151. The apparatus of claim 149, wherein atleast one integrated circuit of the one or more integrated circuits isformed by a Bi-CMOS process.
 152. The apparatus of claim 149, whereinthe integrated circuit of the integrated circuit design is formed by aBipolar process.
 153. The apparatus of claim 149, wherein the integratedcircuit of the integrated circuit design is formed by a Gallium-Arsenideprocess.
 154. The apparatus of claim 149, wherein the integrated circuitof the integrated circuit design is formed by a Silicon-on-Insulatorprocess.
 155. The apparatus of claim 149, wherein the one or more cellsincludes at least one standard cell
 156. The apparatus of claim 149,wherein the one or more cells includes at least one gate array cell.157. The apparatus of claim 149, wherein the one or more cells includesat least one analog cell.
 158. The apparatus of claim 149, wherein theone or more cells includes at least one analog mixed signal cell. 159.The apparatus of claim 149, wherein the one or more cells includes atleast one analog and digital cell.
 160. The apparatus of claim 149,wherein the one or more cells includes at least one functional blockcell.
 161. The apparatus of claim 149, wherein the angle is about 45degrees.
 162. An electrical apparatus, comprising: one or moreintegrated circuits designed at least partly with a first plurality ofone or more cells, the first plurality of one or more cells having afirst plurality of one or more structures on one or more edges of thefirst plurality of one or more cells, wherein the first plurality of oneor more cells is adapted to be positioned by a second plurality of oneor more cells, the second plurality of one or more cells having a secondplurality of one or more structures on one or more edges of the secondplurality of one or more cells, such that at least one structure of thefirst plurality of one or more structures overlaps at least onestructure of the second plurality of one or more structures.
 163. Theapparatus of claim 162, wherein at least one integrated circuit of theone or more integrated circuits is formed by a CMOS process.
 164. Theapparatus of claim 162, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Bi-CMOS process.
 165. Theapparatus of claim 162, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Bipolar process.
 166. Theapparatus of claim 162, wherein at least one integrated circuit of theone or more integrated circuits is formed by a Gallium-Arsenide process.167. The apparatus of claim 162, wherein at least one integrated circuitof the one or more integrated circuits is formed by aSilicon-on-Insulator process.
 168. The apparatus of claim 162, whereinthe one or more cells includes at least one standard cell
 169. Theapparatus of claim 162, wherein the one or more cells includes at leastone gate array cell.
 170. The apparatus of claim 162, wherein the one ormore cells includes at least one analog cell.
 171. The apparatus ofclaim 162, wherein the one or more cells includes at least one analogmixed signal cell.
 172. The apparatus of claim 162, wherein the one ormore cells includes at least one analog and digital cell.
 173. Theapparatus of claim 162, wherein the one or more cells includes at leastone functional block cell.